The present invention relates to memory devices, and in particular, to a reading circuit for a non-volatile memory.
The present invention relates to memory It is well known that to read a cell within a matrix of non-volatile memory cells, i.e., for determining whether a given cell is in one of two binary logic states, appropriate voltages have to be applied between the electrodes of that cell. The cells are arranged in rows and columns and are connected to each other by row and column conductors. These conductors, also respectively known as word lines and bit lines, make it possible for each individual cell to be biased for reading.
When a cell has been selected and biased in this manner, it can be read by a reading circuit that determines whether or not the appropriate column conductor (bit line) carries a current at that moment. A given cell of a memory of the EEPROM type (electrically erasable and programmable read-only memory) is conventionally considered to be programmed or in a logic state 1 when it carries a current, and erased or in a logic state 0 when it does not carry a current.
FIG. 1 schematically illustrates a known reading circuit, indicated overall by the reference number 10. This reading circuit is as described, for example, in Italian Patent Application No. 1999000002119, filed on Oct. 11, 1999 and which is incorporated herein by reference in its entirety and is assigned to the assignee of the present invention.
The reading circuit 10 is associated with a matrix 11 of non-volatile memory cells interconnected by bit lines and word lines. A cell 12 is identified by the intersection of a bit line BL and a word line WL. Column decoding circuits 8 activate the bit lines one at a time. Row decoding circuits 9 activate the word lines one at a time. A memory cell is selected by applying appropriate voltages between its electrodes, and is then read by circuit 10.
Each bit line has a parasitic capacitance indicated by CBL, which is the sum of the input capacitances of the column cells, the capacitance of the selection transistor of the column decoding circuit and the capacitance of the conductor that connects the gate electrodes of the column cells. The first task of the reading circuit 10 is to charge the bit line capacitance CBL. Only after the voltage applied to the capacitance CBL has exceeded a predetermined level will it become possible to read the selected cell.
Circuit 10 includes a detector for every bit line capable of sensing the current carried by the line. This detector comprises an N-channel MOS transistor, indicated by T1, that is connected to the bit line and to the positive pole VDD of a voltage source (whose negative pole, indicated by the ground symbol, is connected to the source electrodes of the matrix cells).
The source electrode of transistor T1 is connected not only with the bit line BL, but also with the input of an inverter stage INV1 that has its output connected to the gate electrode of the same transistor T1. The inverter stage INV1 includes a pair of complementary MOS transistors, or more precisely, an N-channel MOS transistor TN1 and a P-channel transistor TP1 connected as shown in the drawing. The gate electrode of transistor TP1 is connected to a constant-voltage source VP.
The reading circuit 10 also comprises a reference voltage generator 14 that comprises an N-channel MOS transistor T0 and an inverter stage INV0 made up of an N-channel MOS transistor TN0 and a P-channel MOS transistor TP0. The transistors T0, TN0 and TP0 are connected to each other and to the external voltage sources VDD and VP in the same way as the transistors T1, TN1 and TP1 are connected. The reference voltage generator 14 also comprises a constant current generator G0 that is connected between the source electrode of transistor T0 and ground.
Using appropriate connections that are well known to a person skilled in the art, the reading terminal of the detector, i.e., the gate electrode of the transistor associated with each bit line, can be connected to an input terminal of a comparator 16. For purposes of simplifying the figures, the gate electrode of the transistor T1 and the electrode indicated in the drawing by MAT are connected directly to the input terminal of the comparator 16. The gate electrode REF of the transistor T0 is connected to another input terminal of the comparator 16. The output terminal OUT of the comparator also forms the output of the reading circuit 10.
Once the circuit is operating in steady conditions when a cell is selected for reading, such as cell 12, for example, the current passing through the selected cell will also pass through the transistor T1. Since the transistor TN1 is in a constant current biasing condition due to the constant voltage VP applied to the gate terminal of the transistor TP1, the gate electrode of the transistor T1, i.e., the node MAT, will be at a voltage level that depends on this current.
Voltage generator 14 operates in a manner that is similar to that of the current detector described above, but since the current of generator G0 is constant, the gate electrode of transistor T0, i.e., the node REF, will remain at a constant voltage level. The components of generator 14 are dimensioned in such a manner that this constant voltage level will be between the two voltage levels that the node MAT can assume according to whether the associated cell is conducting or not.
Consequently, if the current passing through bit line BL is such that the voltage VMAT of the node MAT will be greater than reference voltage VREF on node REF, the output terminal OUT of comparator 16 will be in a first state corresponding to that of the programmed cell. Otherwise, the output terminal OUT will be in a second state corresponding to that of the non-programmed cell.
As already mentioned, the conditions described above refer to steady operating conditions. Let us now consider the dynamic behavior of the circuit during the reading. At the beginning of the reading the node MAT is substantially at the voltage VDD, the node TREF is substantially at a ground potential (zero), and the node BL likewise is at a ground potential because the capacitance CBL will be without a charge. At the beginning, the current passing through the transistor T1 is only such as is necessary to charge the capacitance CBL. This is because the cell, even if it is programmed, i.e., capable of conducting, is not yet biased in such a way as to conduct because its drain voltage is too low.
In this initial phase there can occur critical operating conditions that may cause the voltage of the node MAT to be lower than it would be in steady conditions. This is due to the fact that transistor T1 and inverter INV1 are interconnected in such a way as to form a feedback loop that, even though it assures that the memory can be read very rapidly, may also create a transitory phenomenon that will cause the potential of node MAT to be smaller than its steady-condition value (undershooting). When this happens during the reading of a programmed cell, the node MAT can even arrive at a voltage smaller than the reference voltage VREF, in which case it will provide the comparator with an input signal that does not correspond to that of a programmed cell, but rather to the signal of an erased cell.
An analysis of the circuit system leads one to note that the phenomenon that has just been described can be attenuated by using a transistor T1 having a large transconductance, i.e., a low resistance while conducting. The charging of the capacitance CBL is effected through low-resistance components and is therefore completed at considerable speed. Unfortunately, however, a large transconductance also implies a low reading sensitivity. In fact, in direct-current operation the reading sensitivity, i.e., the ratio between the voltage of node MAT and the current that passes through transistor T1, is inversely proportional to the transconductance of the transistor.
In view of the foregoing background, an object of the present invention is to provide a reading circuit that will permit the parasitic capacitance of the bit line to be charged very quickly (and thus to have a very brief reading time), and at the same time to assure a very high operating reliability by avoiding the risk of transitory voltage variations that could lead to erroneous readings of the memory cells.
This and other objects advantages and features in accordance with the present invention are provided by a reading circuit for a non-volatile memory comprising a matrix of memory cells, and a plurality of bit lines connected thereto. The reading circuit preferably comprises a comparator having first and second inputs, and an output forming an output of the reading circuit. A reference voltage generator may be connected to the first input of the comparator, and a detection circuit for each bit line includes a reading terminal that is selectively connected to the second input of the comparator. The detection circuit detects a current through a respective bit line.
The detection circuit may comprise a first transistor comprising a gate connected to the reading terminal, and a drain and a source connected in series with the respective bit line. A first inverter stage has an input connected to the source of the first transistor, and an output connected to the gate of the first transistor. A first resistive element is connected between the source of the first transistor and the respective bit line.
A second transistor comprises a gate, and a source and drain connected in series with the respective bit line. A second resistive element is connected between the source of the second transistor and the respective bit line. A second inverter stage has an input connected to the source of the second transistor, and an output connected to the gate of the second transistor.
A third transistor comprises a gate connected to the gate of the second transistor, and a drain and a source connected in parallel with the drain and source of the first transistor. A third inverter stage has an input connected to the respective bit line, and an output connected to the gate of the second transistor.
The input of the third inverter stage may be connected to the respective bit line via a third resistive element, which could also be a portion of the second resistive element. The first, second and third inverter stages may be formed by standard inverters made up of pairs of complementary MOS transistors having common gates as their input, and common drains as their output.